Typical analog and mixed-signal integrated circuits (ICs) have specifications for parametric performance over specific temperature ranges. These parameters may include analog transfer functions (such as gain and offset), analog output magnitude (such as precision reference voltages or currents), time-dependent parameters (such as precision clocks) and the like. Adjustment or calibration of these parameters is often achieved by correlation of the controlled parameter to another parameter that is measured or controlled at a single temperature. For example, a bandgap voltage reference may assume that, for a specific output voltage of the bandgap cell, the temperature coefficient of the voltage is predictable and that the variation of the voltage over temperature will remain within an expected window of variation. Similar schemes are also used for clock generators.
However, there is a practical limit to the level of correlation when second order contributors begin to dominate the accuracy of the specified parameter. Second order parameters may not necessarily exhibit correlation to temperature performance, such as mismatches in the gain stage of a bandgap cell. Another problem with the room versus over temperature correlation is that occasional “flyers” exist that do not fall within the expected band of over temperature operation. These flyers cannot be predicted or identified by a single temperature measurement. The flyers commonly appear as 100-1000 ppm events, which is troublesome for IC vendors who strive to limit defective shipments to well less than 1 ppm.
To attempt to solve these problems, some IC vendors have implemented multi-temperature calibration of ICs by heating a testing environment of many ICs. However, in addition to being very expensive and often impractical, multi-temperature calibration of ICs poses handling and high volume production capacity challenges. Many observers estimate that a performance limitation window of approximately 1% exists for defect free operation over accepted industry temperature ranges based only on room temperature calibration.
Because of this, other IC vendors have implemented multi-temperature calibration of ICs by heating the chips internal to the packages. Generally, this is accomplished by dissipating heat in the die so that the chip temperature is elevated to a higher temperature than the ambient temperature. However, typical methods to implement this technique involve forcing current into or sinking current from sub-circuits that are not primarily designed to serve as heaters and are not normally in a highly dissipative state, often resulting in electrical stress on these sub-circuits.
In addition, using these conventional internal heating methods often results in uneven heating of the die from one or more point sources of heat on the chip. This may create thermal gradients that can modify the actual circuit operation, adversely affecting test results. Also, internal heating methods typically use an externally generated energy pulse and then, based on a predicted time, remove the pulse to perform measurements and adjustments at the elevated temperature. The thermal state in the silicon is therefore dynamic as the chip cools most rapidly immediately following the removal of the heating energy. That is, there is no steady-state equilibrium for the elevated chip temperature. The heating is either open-loop, which is prone to error and is highly sensitive to changes in the packaging process and thermal environment, or relies on a sense element that can be artificially modulated by the high currents in the heater path. This has the disadvantage that the chip is decreasing in temperature while the measurements are being made, possibly resulting in errors for temperature-dependent parameters.
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